A continuing goal of the semiconductor industry is to increase the transistor density of integrated circuits (ICs). In order to accomplish this, transistor sizes must be further downscaled. However, traditionally used complementary metal-oxide semiconductor (CMOS) transistors suffer from difficulties at the nanometer scale. A proposed alternative for achieving denser ICs is to use twin-gated vertical slit field effect transistors (VeSFETs). Our investigation focuses on studying implementations of a Threshold Logic Latch (TLL) realized using a VeSFET- based design paradigm. Making use of the circuit simulator HSPICE, we studied the performance of a TLL circuit design that was mapped onto a basic canvas and chain canvas. After designing cell layouts that realized the TLL, we extracted the parasitic capacitances for both designs to investigate the impact of the design on the propagation delay and robustness of the circuit. We demonstrate through simulation that the VeSFET-based TLL circuit functions as expected when parasitic capacitances are included. While the basic canvas design had a smaller footprint area, the chain canvas design showed a smaller propagation delay.