The mainstream of today’s semiconductor industry is based on bulk-Complementary Metal-Oxide-Semiconductor (CMOS) technology; however, bulk-CMOS technology will eventually run out of stream due to difficulties in scaling. A novel twin-gate transistor—Vertical Slit Field Effect Transistor (VeSFET) may be an alternative. VeSFET transistors are organized into arrays (canvases) and circuits are implemented by configuring metal wires. Herein, we investigate the pros and cons of two VeSFET canvases—basic canvas and chain canvas for Static Random Access Memory (SRAM) design. We extract the parasitic capacitance for different SRAM cell layouts and study the capacitance impact on the performance and robustness of the SRAM by HSPICE simulation. The simulation results show that chain canvas based design will have an improvement in access time and an improvement in noise margin than a basic canvas based design. However, the footprint area of the chain canvas based design is much greater.